The invention relates generally to data transfer systems and relates more particularly to a system for transferring data between two electronic memories.
A growing class of problems, such as seismic processing, numerical analysis, image processing, and signal processing, require a computer capable of performing operations involving multidimensional arrays of data stored in a computer memory.
The array may represent, for example, a matrix, and the operations performed include matrix-matrix multiply, matrix inversion, and so on.
The data in a two-dimensional array is represented by D.sub.i,j where the index i represents the row number and k the column number of the location in the array of the data element. Typically, the array is stored in one long block of storge elements in a computer memory. For example, the first column of an M.times.M array is stored in storage elements START to START+M. Thus, subsequent elements in the same column may be stored in physically adjacent, sequentially addressed, storage elements and subsequent elements in the same row are spaced by M storage locations.
A random access memory (RAM) is characterized by a minimum access time indicating the interval between a request for data and the receipt of the first data. The memory cycle time is the time interval between accesses.
A RAM may have a block access mode as well as random access mode. The block access R/W mode is utilized to decrease the cycle time of the RAM. In block access, N sequentially addressed words are serially transferred between the main RAM and a system bus. The cycle time is reduced below the random access time for all words in the block following the first word. The block access requires a set up time. However, once the block access is set up the cycle time of the block access mode is less than the random mode. For example, a RAM with a random access time of 300 ns may have a 100 ns cycle time in the block access mode with the block set up time being 600 ns.
Thus, if a sequence of words is to be accessed the block mode may be utilized to decrease the overall access time for the block.
In many applications, several, e.g. four, parallel RAM elements are coupled to a parallel bus to form a system memory. Each address is provided to every RAM. If each RAM element transfers a two system word data element between its I/O port and the system bus in response to an address signal, then a wide word comprising eight processor words is transferred between the main RAM I/O port and the system bus. Each processor word is carried on a word-segment of the bus.
The sections of a given wide word stored in each RAM segment have identical addresses. Accordingly, a single address accesses the wide word in the main RAM.
In many instances, matrix, or other array operations only require the data elements, S.sub.i,j, forming a subarray embedded in the array D. Typically, these elements, S.sub.i,j, are transferred from the main array to a buffer of the matrix processor. Alternatively, the results of an operation may modify only a subarray of the stored array. Only the modified elements need be written into the system RAM.
The parallel access of wide words, including several system words, on each memory cycle provides for a very high data transfer rate from the memory.
However, for a subarray dispersed in the data array, a large number of unneeded data words, or fluff, will be transferred. If subarray data and fluff transferred from the system are loaded into a processor buffer several problems result. For example, the buffer must be much larger than needed just to accommodate subarray data. Additionally, before processing the subarray data, the subarray data must be separated from the fluff.
Additionally, for a given subarray, a read or write operation to the system memory may be accomplished by various combinations of random or block accesses. However, certain ones of those combinations, depending on the specific parameters of the subarray and other system constraints, will minimize the cycle time to transfer the words in the subarray between the system memory and the buffer.
Accordingly, a system for separating fluff from subarray data while providing the high data transfer rates achievable in a parallel system having a block access mode is needed to facilitate high speed processing of arrays and subarrays of data.